1. Field of the Invention
This invention relates to delay generators generally, and more particularly, to delay generators used in clock recovery circuitry of data communication receivers, such as high-speed optical data links.
2. Description of the Prior Art
Most data communication systems require the synchronization of a local sampling clock to an incoming digital data stream to optimally sample the incoming data stream and control the decoding thereof. Typically, the synchronization must extract the local sampling clock from the incoming digital data itself. With many very high-speed systems, the synchronizing process is complicated by the data format of the digital data stream having relatively few data transitions from which a local clock can be derived, e.g., non-return-to-zero (NRZ) coding. The NRZ format allows for a relatively large amount of data which may be transmitted within a given bandwidth, the bandwidth being dictated by regulation or tariff, transmission media capacity, or the capacity of the electronics coupling to the transmission media.
At very high speeds (e.g., 10.sup.9 -10.sup.10 bits per second, referred to here as 1-10 Giga-bits per second, or Gbs), the traditional methods of deriving the local clock are not sufficient, because of many factors, such as, delay stability with time and temperature, cost, delay symmetry, or physical size. For example, as shown in FIG. 14, page 157, of Optical Wideband Transmission Systems by Clemens Baack, Dr.-Ing., 1986, the matched filter/threshold comparator/differentiator/fullwave rectifier arrangement for clock recovery suffers from considerable phase jitter and is difficult to implement in integrated form for the 1-10 Gbs range. The matched filter/square law/high-pass filter arrangement in FIG. 15, also on page 157 of the above-identified reference, is difficult to implement in integrated form for the 1-10 Gbs range due to the strict requirements for the square law function. In addition, the high-pass filter would be composed of a surface acoustic-wave device (SAW) at high bit rates, such as above 1 Gbs, and is not integratable with the other circuitry. However, at very high bit rates, such as at 10 Gbs, the SAW device would not be practical or cost effective to manufacture. At these very high bit rates, the delay-and-multiply technique shown in FIG. 14-1(b) of Digital Communications by Satelliteby J. J. Spilker, Jr., 1977, may be practical so long as the delay generator can provide a stable delay (of one-half the bit period) over temperature and aging. Preferably, the delay generator should be monolithically integratable with the other electronics of the receiver, unlike the SAW device which cannot be integrated therewith. It is therefore desirable to provide a delay generator which is readily integratable with other electronic circuits used for a receiving system.
It is further desirable to provide such a delay generator that is both relatively inexpensive to manufacture and have reasonably stable delays with temperature and aging. Further, such a delay generator should be adaptable to operate over a relatively wide range of delays. In particular, the delay generator should be able to provide the relatively very short delays necessary for very high-speed digital communication systems, such as high-speed optical data links and the like.